In System Verilog UVM, the interface present in TLM ports for communication between sequences and drivers (uvm_sqr_if_base
) offers flexibility. For pulling requests, I'll summarize the four options in this table:
blocking item_done get_next_item() yes no try_next_item() no no get() yes yes peek() yes no
... where blocking indicates that if you call the method, but no sequence is ready to provide data, then the task will BLOCK and wait until data is ready and can and will be returned.
... where item_done indicates that the method also calls item_done()
after successfully pulling an item from the sequence.
What's the difference between peek()
and get_next_item()
then?
Consider these two code snippets from two imaginary drivers ...
while(1) begin: loop1 while(1) begin: loop2 seq_item_port.get_next_item(req); seq_item_port.peek(req); process(req); process(req); seq_item_port.item_done(); seq_item_port.item_done(); end: loop1 end: loop2
What's the difference? Why are there two methods for accomplishing the same thing? It doesn't seem to be TLM1 vs TLM2 styles.
https://stackoverflow.com/questions/67410914/whats-the-difference-between-uvm-sqr-if-basepeek-and-uvm-sqr-if-baseget-n May 06, 2021 at 10:05AM
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