How does MSI-X triggers interrupt handlers? Is there a need to poll the chosen memory address?

I have a small kernel which is booted with UEFI. I'm using QEMU for virtualization. I want to write a xHCI driver to support USB keyboards in my kernel. I'm having trouble to find concise and clear information. I "found" the xHCI in my kernel. I have a pointer to its PCI configuration space. It is MSI-X capable. I want to use MSI-X but I'm having trouble to understand how that works with the xHCI and USB.

My problem is that normally osdev.org is quite informational and has the basis I need to implement some functionality. In the case of MSI-X, it doesn't seem to be the case. I'm having a hard time to make the link between all the information I have on osdev.org with the MSI-X functionality.

So basically, I find the MSI-X table and then I set some addresses there to tell the xHCI PCI device to write to that address to trigger an interrupt. But is an interrupt handler called at some point? Do I need to poll this address to determine if an interrupt occured? I would have thought that the Vector Control field in the MSI-X table let me set an interrupt vector but all the bits are reserved.

EDIT

I found the following stackoverflow Q&A which partially answers my question: Question about Message Signaled Interrupts (MSI) on x86 LAPIC system.

So basically, the low byte of the data register contains the vector to trigger and the message address register contain the lAPIC id to trigger. I still have some questions.

1. Why does the "Message Address register contains fixed top of 0xFEE".

2. What are the RH, DM and XX bits in the Message Address register?

3. How does this work with the lAPIC? Basically, how does it trigger interrupts in the lAPIC. Is it a special feature of PCI devices which allows them to trigger interrupts in the lAPIC. Or is it simply that PCI devices write to memory mapped registers of the lAPIC with some specific data which triggers an interrupt. Because normally the lAPIC is accessed from within the core at an address which is the same for every lAPIC. Is it some kind of inter-processor interrupt from outside the CPU?

https://stackoverflow.com/questions/67028147/how-does-msi-x-triggers-interrupt-handlers-is-there-a-need-to-poll-the-chosen-m April 10, 2021 at 04:54AM