Register and integer comparison in system verilog

I am facing an interesting issue in systemVerilog where the comparison with a register isnt working.

always @(posedge p_tick) begin      if (~reset) begin          red_reg <= 4'b0;          green_reg <= 4'b0;          blue_reg <= 4'b0;      end else begin          rbg <= rbg;                    if (h_count_reg == 0) begin                    rbg <= 12'b100000000000;          end                  if (h_count_reg == i) begin          i = i+80;                    rbg <= rbg + 12'b000000010000;          end          end  end    

In the above code h_count_reg is 0 works fine. If I change 0 to any different number it will work as expected. However, if I replace that number with a variable ( which is "i", declared on top of my module as int i = 80;) the code seems to ignore it which is weird. Replacing the i variable with any number will work. How come?

Thank you in advance!

Joe

https://stackoverflow.com/questions/66524571/register-and-integer-comparison-in-system-verilog March 08, 2021 at 01:07PM