How to properly read "partially undefined" signals in VHDL

I have a question that it might be straightforward for someone more experienced than I in VHDL programming.

I have a 160wx64 bits RAM memory with masking. The masking allows me to write in, for example, only the 32 first bits of a word. My Test Bench basically does the following:

1. I write 18 bits in the MSB part of the first address.
2. I read the value on that address to check that the value was properly written.

When reading, I do get the value, but partially undefined, like the following:

"101000000000000001UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU"

This makes sense, since I applied a mask to only write on the MSB 18 bits. However, when trying to take this signal into another one in order to output it, I got problems, because in this signal I only got "UUUUUUUUUUUUUUUUUU" (I've also tried reading the 18 LSB bits, just in case they were inverted, but didn't work). The way I do it is by declaring a variable withing the FSM process:

if (mask_reg = mask1) then     ram_DO_tmp := ram_DxDO(63 downto 46);     outReg_next <= ram_DO_tmp;  --63 to 46  

Before trying this workaround, I was assignating the masked signal directly to the register. Either way, the result was not the desired one. In the image below "outReg" is a 18 bits register where I try to store the content of the masked output signal coming from the RAM "DataxDO"

I hope that was clear and that someone can help, I'll appreciate it.

Regards, Sergio

https://stackoverflow.com/questions/66513095/how-to-properly-read-partially-undefined-signals-in-vhdl March 07, 2021 at 12:07PM