VHDL counter simulated using a test bench giving 'Uninitialized' for the output, how is this resolved?

Below is a counter that is designed to represent an 8 bit binary number with 8 LEDs, it is being simulated using a test bench, however when running the simulation the output simply shows UU for the led.

Here is the main entity that I wish to test:

use IEEE.STD_LOGIC_1164.all;  use IEEE.STD_LOGIC_unsigned.all;    entity Lab_3_Source_File is   generic(N_BITS : integer := 8);   port(   btnd : in STD_LOGIC ;   clk : in STD_LOGIC;   led : out STD_LOGIC_VECTOR(7 downto 0)   );  end Lab_3_Source_File;    architecture counter of Lab_3_Source_File is  signal count: STD_LOGIC_VECTOR(7 downto 0);    begin    process(clk, btnd)  begin   if btnd = '1' then   count <= (others => '0');   elsif rising_edge(clk) then   count <= count + 1;   end if;  end process;     led <= count;  end counter;  

Here is the test bench that I have tried to map to the main entity:

use IEEE.STD_LOGIC_1164.ALL;      entity Count_TestBench is    end Count_TestBench;    architecture Behavioral of Count_TestBench is                                                          signal btnd, clk : STD_LOGIC;      signal led : STD_LOGIC_VECTOR(7 downto 0);  begin         UUT : entity work.Lab_3_Source_File port map (btnd => btnd,clk => clk,led => led);         process      begin          btnd<='1';          btnd<='0';              led<= (others => '0');                     for i in 1 to 100 loop              clk<='1';              wait for 10 ns;              clk<='0';              wait for 10 ns;              led<=led;          end loop;                end process;  end Behavioral;  

Please could somebody help me understand how to enable the simulation to display the led output incrementing?

EDIT:

Set btnd to 1 in the test bench to initialise the led, following the answer from mkrieger1, the led output is still at U following this change.

https://stackoverflow.com/questions/65545587/vhdl-counter-simulated-using-a-test-bench-giving-uninitialized-for-the-output January 03, 2021 at 08:39AM