Assignment one item from two?

I've been studying Verilog for a while and recently came across a kind of statement that I do not understand. Here is an example:

reg s_axis_data_tready_reg = 1'b0, s_axis_data_tready_next;  

Looks like a concatenation but doesn't have the curly brackets surrounding the two items separated by a comma. This statement compiles with no error. What does this statement do?

https://stackoverflow.com/questions/65854826/assignment-one-item-from-two January 23, 2021 at 09:19AM